ICM42670_Driver_STM32_ESP32/ICM42670__registermap_8h_source.html

#ifndef ICM42670_REGISTERMAP_H

#define ICM42670_REGISTERMAP_H


#ifdef __cplusplus

extern "C" {

#endif


#include <stdint.h>


/* Device identity. */

#define ICM42670_REG_WHO_AM_I 0x75U

#define ICM42670_WHO_AM_I_VALUE 0x67U


/* User bank 0: basic status and control. */

#define ICM42670_REG_MCLK_RDY 0x00U

#define ICM42670_REG_DEVICE_CONFIG 0x01U

#define ICM42670_REG_SIGNAL_PATH_RESET 0x02U

#define ICM42670_REG_DRIVE_CONFIG1 0x03U

#define ICM42670_REG_DRIVE_CONFIG2 0x04U

#define ICM42670_REG_DRIVE_CONFIG3 0x05U

#define ICM42670_REG_INT_CONFIG 0x06U


#define ICM42670_REG_TEMP_DATA1 0x09U

#define ICM42670_REG_TEMP_DATA0 0x0AU

#define ICM42670_REG_ACCEL_DATA_X1 0x0BU

#define ICM42670_REG_ACCEL_DATA_X0 0x0CU

#define ICM42670_REG_ACCEL_DATA_Y1 0x0DU

#define ICM42670_REG_ACCEL_DATA_Y0 0x0EU

#define ICM42670_REG_ACCEL_DATA_Z1 0x0FU

#define ICM42670_REG_ACCEL_DATA_Z0 0x10U

#define ICM42670_REG_GYRO_DATA_X1 0x11U

#define ICM42670_REG_GYRO_DATA_X0 0x12U

#define ICM42670_REG_GYRO_DATA_Y1 0x13U

#define ICM42670_REG_GYRO_DATA_Y0 0x14U

#define ICM42670_REG_GYRO_DATA_Z1 0x15U

#define ICM42670_REG_GYRO_DATA_Z0 0x16U

#define ICM42670_REG_TMST_FSYNCH 0x17U

#define ICM42670_REG_TMST_FSYNCL 0x18U


/* User bank 0: power, scale, ODR, and filter configuration. */

#define ICM42670_REG_PWR_MGMT0 0x1FU

#define ICM42670_REG_GYRO_CONFIG0 0x20U

#define ICM42670_REG_ACCEL_CONFIG0 0x21U

#define ICM42670_REG_TEMP_CONFIG0 0x22U

#define ICM42670_REG_GYRO_CONFIG1 0x23U

#define ICM42670_REG_ACCEL_CONFIG1 0x24U


/* User bank 0: APEX/WOM/FIFO/interrupt basics. */

#define ICM42670_REG_APEX_CONFIG0 0x25U

#define ICM42670_REG_APEX_CONFIG1 0x26U

#define ICM42670_REG_WOM_CONFIG 0x27U

#define ICM42670_REG_FIFO_CONFIG1 0x28U

#define ICM42670_REG_FIFO_CONFIG2 0x29U

#define ICM42670_REG_FIFO_CONFIG3 0x2AU

#define ICM42670_REG_INT_SOURCE0 0x2BU

#define ICM42670_REG_INT_SOURCE1 0x2CU

#define ICM42670_REG_INT_SOURCE3 0x2DU

#define ICM42670_REG_INT_SOURCE4 0x2EU

#define ICM42670_REG_INTF_CONFIG0 0x35U

#define ICM42670_REG_INTF_CONFIG1 0x36U

#define ICM42670_REG_INT_STATUS_DRDY 0x39U

#define ICM42670_REG_INT_STATUS 0x3AU

#define ICM42670_REG_INT_STATUS2 0x3BU

#define ICM42670_REG_INT_STATUS3 0x3CU

#define ICM42670_REG_FIFO_COUNTH 0x3DU

#define ICM42670_REG_FIFO_COUNTL 0x3EU

#define ICM42670_REG_FIFO_DATA 0x3FU


/* User bank 0: indirect MREG access window. */

#define ICM42670_REG_BLK_SEL_W 0x79U

#define ICM42670_REG_MADDR_W 0x7AU

#define ICM42670_REG_M_W 0x7BU

#define ICM42670_REG_BLK_SEL_R 0x7CU

#define ICM42670_REG_MADDR_R 0x7DU

#define ICM42670_REG_M_R 0x7EU


/* MREG bank identifiers and MREG1 register addresses. */

#define ICM42670_MREG1 0x00U

#define ICM42670_MREG1_REG_TMST_CONFIG1 0x00U

#define ICM42670_MREG1_REG_FIFO_CONFIG5 0x01U

#define ICM42670_MREG1_REG_FIFO_CONFIG6 0x02U

#define ICM42670_MREG1_REG_FSYNC_CONFIG 0x03U

#define ICM42670_MREG1_REG_INT_CONFIG0 0x04U

#define ICM42670_MREG1_REG_INT_CONFIG1 0x05U

#define ICM42670_MREG1_REG_SENSOR_CONFIG3 0x06U

#define ICM42670_MREG1_REG_FDR_CONFIG 0x66U


/* Useful contiguous burst lengths. */

#define ICM42670_TEMP_DATA_LEN 2U

#define ICM42670_ACCEL_DATA_LEN 6U

#define ICM42670_GYRO_DATA_LEN 6U

#define ICM42670_ACCEL_GYRO_TEMP_LEN 14U


/* MCLK_RDY bits. */

#define ICM42670_MCLK_RDY_MASK 0x08U


/* DEVICE_CONFIG bits. */

#define ICM42670_DEVICE_CONFIG_SOFT_RESET 0x01U

#define ICM42670_DEVICE_CONFIG_SPI_MODE_0 0x00U

#define ICM42670_DEVICE_CONFIG_SPI_MODE_3 0x10U


/* SIGNAL_PATH_RESET bits. */

#define ICM42670_SIGNAL_PATH_FIFO_FLUSH 0x04U


/* FIFO_CONFIG1 bits. */

#define ICM42670_FIFO_CONFIG1_MODE_MASK 0x02U

#define ICM42670_FIFO_CONFIG1_MODE_STREAM 0x00U

#define ICM42670_FIFO_CONFIG1_MODE_STOP_ON_FULL 0x02U

#define ICM42670_FIFO_CONFIG1_BYPASS_MASK 0x01U

#define ICM42670_FIFO_CONFIG1_BYPASS_DISABLE 0x00U

#define ICM42670_FIFO_CONFIG1_BYPASS_ENABLE 0x01U


/* FIFO_CONFIG2 and FIFO_CONFIG3 bits. */

#define ICM42670_FIFO_CONFIG2_WM_LOW_MASK 0xFFU

#define ICM42670_FIFO_CONFIG3_WM_HIGH_MASK 0x0FU

#define ICM42670_FIFO_WATERMARK_MAX 0x0FFFU


/* PWR_MGMT0 field values. */

#define ICM42670_PWR_ACCEL_LP_CLK_WUOSC 0x00U

#define ICM42670_PWR_ACCEL_LP_CLK_RC 0x80U

#define ICM42670_PWR_IDLE 0x10U

#define ICM42670_PWR_GYRO_OFF 0x00U

#define ICM42670_PWR_GYRO_STANDBY 0x04U

#define ICM42670_PWR_GYRO_LN 0x0CU

#define ICM42670_PWR_ACCEL_OFF 0x00U

#define ICM42670_PWR_ACCEL_LP 0x02U

#define ICM42670_PWR_ACCEL_LN 0x03U

#define ICM42670_PWR_ACCEL_GYRO_LN                                             \

  (ICM42670_PWR_GYRO_LN | ICM42670_PWR_ACCEL_LN)


/* GYRO_CONFIG0 and ACCEL_CONFIG0 field masks. */

#define ICM42670_GYRO_CONFIG0_FS_SEL_MASK 0x60U

#define ICM42670_GYRO_CONFIG0_ODR_MASK 0x0FU

#define ICM42670_ACCEL_CONFIG0_FS_SEL_MASK 0x60U

#define ICM42670_ACCEL_CONFIG0_ODR_MASK 0x0FU

#define ICM42670_GYRO_CONFIG1_UI_FILT_BW_MASK 0x07U

#define ICM42670_ACCEL_CONFIG1_UI_FILT_BW_MASK 0x07U


/* APEX_CONFIG1 and WOM_CONFIG bits. */

#define ICM42670_APEX_CONFIG1_FEATURE_ENABLE_MASK 0x78U

#define ICM42670_WOM_CONFIG_WOM_EN 0x01U


/* INTF_CONFIG0 bits. */

#define ICM42670_INTF_CONFIG0_FIFO_COUNT_FORMAT_MASK 0x40U

#define ICM42670_INTF_CONFIG0_FIFO_COUNT_FORMAT_BYTES 0x00U

#define ICM42670_INTF_CONFIG0_FIFO_COUNT_FORMAT_RECORDS 0x40U

#define ICM42670_INTF_CONFIG0_FIFO_COUNT_ENDIAN_MASK 0x20U

#define ICM42670_INTF_CONFIG0_SENSOR_DATA_ENDIAN_MASK 0x10U


/* FIFO packet header bits. */

#define ICM42670_FIFO_HEADER_MSG 0x80U

#define ICM42670_FIFO_HEADER_ACCEL 0x40U

#define ICM42670_FIFO_HEADER_GYRO 0x20U

#define ICM42670_FIFO_HEADER_20 0x10U

#define ICM42670_FIFO_HEADER_TIMESTAMP_FSYNC_MASK 0x0CU

#define ICM42670_FIFO_HEADER_ODR_ACCEL 0x02U

#define ICM42670_FIFO_HEADER_ODR_GYRO 0x01U


/* MREG1 TMST_CONFIG1 bits. */

#define ICM42670_TMST_CONFIG1_ON_SREG_EN 0x10U

#define ICM42670_TMST_CONFIG1_RES_16US 0x08U

#define ICM42670_TMST_CONFIG1_DELTA_EN 0x04U

#define ICM42670_TMST_CONFIG1_FSYNC_EN 0x02U

#define ICM42670_TMST_CONFIG1_TMST_EN 0x01U


/* MREG1 FSYNC_CONFIG bits. */

#define ICM42670_FSYNC_CONFIG_UI_SEL_MASK 0x70U

#define ICM42670_FSYNC_CONFIG_UI_SEL_SHIFT 4U

#define ICM42670_FSYNC_CONFIG_UI_FLAG_CLEAR_SEL 0x02U

#define ICM42670_FSYNC_CONFIG_POLARITY_FALLING 0x01U


/* MREG1 FIFO_CONFIG5 bits. */

#define ICM42670_FIFO_CONFIG5_WM_GT_TH 0x20U

#define ICM42670_FIFO_CONFIG5_RESUME_PARTIAL_RD 0x10U

#define ICM42670_FIFO_CONFIG5_HIRES_EN 0x08U

#define ICM42670_FIFO_CONFIG5_TMST_FSYNC_EN 0x04U

#define ICM42670_FIFO_CONFIG5_GYRO_EN 0x02U

#define ICM42670_FIFO_CONFIG5_ACCEL_EN 0x01U


/* MREG1 FIFO_CONFIG6 bits. */

#define ICM42670_FIFO_CONFIG6_EMPTY_INDICATOR_DIS 0x10U

#define ICM42670_FIFO_CONFIG6_RCOSC_REQ_ON_FIFO_THS_DIS 0x01U


/* MREG1 INT_CONFIG0 bits. */

#define ICM42670_INT_CONFIG0_UI_DRDY_INT_CLEAR_MASK 0x30U

#define ICM42670_INT_CONFIG0_FIFO_THS_INT_CLEAR_MASK 0x0CU

#define ICM42670_INT_CONFIG0_FIFO_FULL_INT_CLEAR_MASK 0x03U

#define ICM42670_INT_CONFIG0_CLEAR_ON_STATUS_READ 0x00U

#define ICM42670_INT_CONFIG0_FIFO_THS_CLEAR_ON_FIFO_READ 0x08U

#define ICM42670_INT_CONFIG0_FIFO_FULL_CLEAR_ON_FIFO_READ 0x02U


/* MREG1 INT_CONFIG1 bits. */

#define ICM42670_INT_CONFIG1_TPULSE_DURATION_8US 0x40U

#define ICM42670_INT_CONFIG1_ASYNC_RESET 0x10U


/* MREG1 SENSOR_CONFIG3 bits. */

#define ICM42670_SENSOR_CONFIG3_APEX_DISABLE 0x40U


/* Common config bytes. */

#define ICM42670_GYRO_CONFIG0_2000DPS_100HZ                                    \

  (ICM42670_GYRO_FS_2000_DPS | ICM42670_ODR_100_HZ)

#define ICM42670_ACCEL_CONFIG0_16G_100HZ                                       \

  (ICM42670_ACCEL_FS_16G | ICM42670_ODR_100_HZ)


/* INT_CONFIG bits. */

#define ICM42670_INT_CONFIG_INT2_LATCHED 0x20U

#define ICM42670_INT_CONFIG_INT2_PUSH_PULL 0x10U

#define ICM42670_INT_CONFIG_INT2_ACTIVE_HIGH 0x08U

#define ICM42670_INT_CONFIG_INT1_LATCHED 0x04U

#define ICM42670_INT_CONFIG_INT1_PUSH_PULL 0x02U

#define ICM42670_INT_CONFIG_INT1_ACTIVE_HIGH 0x01U

#define ICM42670_INT_CONFIG_BOTH_LATCHED_PUSH_PULL_ACTIVE_HIGH                 \

  (ICM42670_INT_CONFIG_INT2_LATCHED | ICM42670_INT_CONFIG_INT2_PUSH_PULL |     \

   ICM42670_INT_CONFIG_INT2_ACTIVE_HIGH | ICM42670_INT_CONFIG_INT1_LATCHED |   \

   ICM42670_INT_CONFIG_INT1_PUSH_PULL | ICM42670_INT_CONFIG_INT1_ACTIVE_HIGH)


/* INT_SOURCE0 bits. */

#define ICM42670_INT_SOURCE0_FSYNC_INT1_EN 0x40U

#define ICM42670_INT_SOURCE0_DRDY_INT1_EN 0x08U

#define ICM42670_INT_SOURCE0_FIFO_THS_INT1_EN 0x04U

#define ICM42670_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02U


/* INT_SOURCE3 bits. */

#define ICM42670_INT_SOURCE3_FSYNC_INT2_EN 0x40U

#define ICM42670_INT_SOURCE3_DRDY_INT2_EN 0x08U

#define ICM42670_INT_SOURCE3_FIFO_THS_INT2_EN 0x04U

#define ICM42670_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02U


/* INT_STATUS_DRDY bits. */

#define ICM42670_INT_STATUS_DRDY_DATA_RDY 0x01U


/* INT_STATUS bits. */

#define ICM42670_INT_STATUS_ST 0x80U

#define ICM42670_INT_STATUS_FSYNC 0x40U

#define ICM42670_INT_STATUS_PLL_RDY 0x20U

#define ICM42670_INT_STATUS_RESET_DONE 0x10U

#define ICM42670_INT_STATUS_FIFO_THS 0x04U

#define ICM42670_INT_STATUS_FIFO_FULL 0x02U

#define ICM42670_INT_STATUS_AGC_RDY 0x01U


#ifdef __cplusplus

}

#endif


#endif /* ICM42670_REGISTERMAP_H */